PCIe technology is set to be leveraged as an important component in the AI infrastructure marketplace. According to the “PCI ...

This collaboration highlights GUC's commitment to deliver comprehensive and innovative design solutions, enabling customers ...

A jury in Wilmington, Delaware, has found that Qualcomm’s latest AI-PC processors – based on the ARM instruction set – are ...

This funding will support the continued development and demonstration of Strategic Radiation Hardened (SRH) high reliability ...

The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in subLVDS mode only, which is defined in the ...

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ... Rambus ...

The 10/100/1G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10/100/1000M Ethernet ...

The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applications such as next—generation, feature-rich ...

The MXL-D-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured as a MIPI ...

The agileLDO is a linear low-dropout voltage regulator (LDO) providing precision and programmable voltage regulation across a wide range of input and output voltages. The regulator architecture ...

Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processors, and peripheral devices. Synopsys’ broad MIPI IP ...

The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-SPI core can operate as a SPI master or slave.